Real-time profile, Thumb / Thumb-2 / DSP / optional VFPv3 FPU and precision, hardware multiply and optional divide instructions, optional parity & ECC for internal buses / cache / TCM, 8-stage pipeline dual-core running lock-step with fault logic / optional as 2 independent cores, low-latency peripheral port (LLPP), accelerator coherency port (ACP) Ġ–64 KB / 0–64 KB, 0–2 of 0–8 MB TCM, opt. Real-time profile, Thumb / Thumb-2 / DSP / optional VFPv3 FPU, hardware multiply and optional divide instructions, optional parity & ECC for internal buses / cache / TCM, 8-stage pipeline dual-core running lockstep with fault logicĠ–64 KB / 0–64 KB, 0–2 of 0–8 MB TCM, opt. Microcontroller profile, Thumb-1, Thumb-2, Saturated, DSP, Divide, FPU (SP), TrustZone, Co-processorīuilt-in cache (with option 2–16 KB), I-cache, no TCM, optional MPU with 16 regions Optional cache, no TCM, optional MPU with 16 regions Microcontroller profile, Thumb-1 (most), Thumb-2 (some), Divide, TrustZone Microcontroller profile, Thumb / Thumb-2 / DSP / optional VFPv5 single and double precision FPU, hardware multiply and divide instructionsĠ−64 KB I-cache, 0−64 KB D-cache, 0–16 MB I-TCM, 0–16 MB D-TCM (all these w/optional ECC), optional MPU with 8 or 16 regions Microcontroller profile, Thumb / Thumb-2 / DSP / optional VFPv4-SP single-precision FPU, hardware multiply and divide instructions, optional bit-banding memory Microcontroller profile, Thumb / Thumb-2, hardware multiply and divide instructions, optional bit-banding memory Microcontroller profile, most Thumb + some Thumb-2, hardware multiply instruction (optional small), OS option adds SVC / banked stack pointer, optional system timer, no bit-banding memory Optional cache, no TCM, optional MPU with 8 regions Microcontroller profile, most Thumb + some Thumb-2, hardware multiply instruction (optional small), optional system timer, optional bit-banding memory Thumb, Jazelle DBX, enhanced DSP instructions, (VFP)Ĩ-stage pipeline, SIMD, Thumb, Jazelle DBX, (VFP), enhanced DSP instructions, unaligned memory accessħ40 532–665 MHz (i.MX31 SoC), 400–528 MHzĩ-stage pipeline, SIMD, Thumb-2, (VFP), enhanced DSP instructionsĩ65 DMIPS 772 MHz, up to 2,600 DMIPS with four processors

Thumb, Jazelle DBX, enhanced DSP instructionsĦ-stage pipeline, Thumb, enhanced DSP instructions, (VFP) ARMv2a added the SWP and SWPB (swap) instructionsĪRMv3 first to support 32-bit memory address space (previously 26-bit).ĪRMv3M first added long multiply instructions (32x32=64).Īs ARM60, cache and coprocessor bus (for FPA10 floating-point unit)ģ-stage pipeline, Thumb, ARMv4 first to drop legacy ARM 26-bit addressingĨ KB unified, MMU with FCSE (Fast Context Switch Extension)ĥ-stage pipeline, Thumb, Jazelle DBX, enhanced DSP instructionsĥ-stage pipeline, static branch prediction, double-bandwidth memoryġ6 KB / 16 KB, MMU with FCSE (Fast Context Switch Extension) Integrated MEMC (MMU), graphics and I/O processor. ARM 코어 ARM 설계 ARM 계열ĪRMv2 added the MUL (multiply) instruction

Cache coherence cortex a9